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Compact Thermal Modeling and Simulations, Software Thermal Sensor Techniques

jbradfield — Thu, 01 Aug 2019 22:27:21 +0000

Compact Thermal Modeling and Simulations, Software Thermal Sensor Techniques jbradfield Thu, 08/01/2019 - 15:27 More Project August 01, 2009

Principle Investigators

Dr. Sheldon Tan (PI),
Dr. Yingbo Hua (co-PIs).

Graduate Students

Hai Wang,
Zou Liu,
Duo Li,
Thom Eguia,
Ruijing Shen,
Shengyang Xu (supervised by Prof. Yingbo Hua),
Wei Wu,
Pu Liu,

Funding support

We appreciate the following funding agencies for their generous supports of this project.

National Science Foundation, “Fast Software Thermal Sensing and Control for Efficient Dynamic Thermal Management”, (CCF- 0541456), 7/1/2006-6/30/2009, co-PI: Sheldon Tan, PI: Jun Yang.
National Science Foundation, “Parameterized Architecture-Level Thermal Modeling and Characterization for Multi-Core Microprocessor Design”, (CCF-0902885), 8/1/09-7/31/12, PI: Sheldon Tan, co-PI: Yingbo Hua.
Semiconductor Research Corporation, “Parameterized Architecture-Level Thermal Modeling and Characterization for Multi-Core Microprocessor Design”, NSF/SRC Multi-core Program (SRC 2009-TJ-1991), Aug.1, 2009 to July 30, PI: Sheldon Tan, Co-PI: Yinbo Hua
UC MICRO Program (via Intel Corporation) (#07-101), “Parameterized Thermal Behavioral Modeling and Simulation for Designing System Platforms”, Sept. 2007 to Aug. 2008, PI: Sheldon Tan
UC MICRO Program (via Intel Corporation) (#08-11), “Parameterized Thermal Behavioral Modeling and Simulation for Designing System Platforms”, Sept. 2008 to Dec. 2009, PI: Sheldon Tan
Intel Corporation, Nov., 2009 to Dec, 2010. PI: Sheldon Tan

Project Descriptions

Background

As more devices are integrated into the single chip with even increasing functionality, today's chips become very hot. A Pentium 4 processor typically burns ~70W within only a 3.2 x 3.2 cm2 die, generating local temperature above boiling point rapidly if the cooling system (which consumes power as well) is not efficient. These trends are resulting in heat fluxes at the chip level of over 100 W/cm2 in some applications. Designing the package for worst-case scenarios is too expensive and not efficient since it increases the cooling and packaging cost dramatically, and the worst cases are rare. With an upper limit of 70-125°C as the maximum allowable chip temperature in many applications, acceptable online thermal management and regulation is a key enabler for next generation integrated electronic systems. Excessive local thermal stress creates reliability problems for the entire system, speeds up the depreciation of expensive computing equipment, reduces the speed of processors, and causes significant leakage power consumption. Sub-threshold leakage of CMOS devices depends greatly on the substrate temperature. Thermal management continues to be identified by the Semiconductor Industries Association Roadmap as one of the five key challenges during the next decade for achieving the projected performance goals of the industry.

In this project, we investigate the efficient thermal simulation and modeling techniques for architecture level thermal profile estimation and hot spot identifications to guide the thermal-aware chip and package design and provide fast thermal estimation for on-chip dynamic thermal management and regulations to mitigate the increasing thermal crisis in today multi-core microprocessors and high-performance integrated systems. We envision a fast thermal simulator, which can be used as soft thermal sensors mitigating the problems with physical sensors for efficient on-chip dynamic thermal management. To address the thermal estimation problems at architecture and package level, we need to address the following aspects (1) Thermal system modeling and characterizations, (2) Fast thermal simulation and analysis techniques, (3) Accurate power estimation at the architecture level. In the past several years, my group has made a number of contributions to those critical areas. First, in the fast thermal simulation and analysis area (2), we proposed a fast thermal moment matching (TMM) algorithm [J1, C1,C2], which can perform transition thermal analysis in linear time and is proven to be well suited for online thermal management and regulations [J2]. The TMM has been used in Intel Corporation for package-level faster thermal simulation and thermal modeling. We further another fast thermal analysis approach, FEKIS, which combines two existing numerical techniques: extended Krylov subspace reduction technique to reduce the thermal circuit complexity and large-step integration method to exploit the piecewise constant power input traces, which is typical in the power traces at the architecture level. The resulting method is 10X faster TMM is better suitable for chip level thermal analysis [J3,C7]. Second, in the thermal system modeling and characterization area, we also proposed a host of new methods to address the thermal modeling problem at the architecture and package levels. This research is concerned about building compact thermal circuits and systems (instead of solving the partial differential thermal diffusion equations) to facilitate fast thermal simulation without loss of accuracy. Different than the traditional methods, where the thermal circuit systems from the given power and temperature information coming from the field solvers and measured data. We tried to build behavioral thermal models without regarding non-essential physical properties of a thermal system. We proposed a pencil-of-function (POF) based thermal modeling techniques for step-function power inputs. The resulting technique is called ThermPOF [J4,C5,C6], which can build the transfer functions from step power input and given temperature. We further extended the ThermPOF, called ParThermPOF, to consider the changing parameters of a package such as thermal conductivities of heat sinks, temperature at different location of the sinks etc. [J6, C8].

To mitigate the restrictions on the power inputs, which must be step functions in the ThermPOF method, we proposed new thermal modeling techniques based on recently proposed subspace identification method. The new method called, ThermSID, allows arbitrary power input in general as the training data. However, overfitting problem (the modeling may identify many no-essential measure errors instead of real system information) typically plaques those identification method. We proposed a cross-validation-like method to mitigate the overfitting issues in the ThermSID [C10,C11,J7]. For subspace based approach, the method however, may suffer predictability problem when the practical power inputs are spatially correlated. Our further study shows that there exists a theoretical spatial rank (or the ranks of signals among different correlated power inputs) requirement to ensure model predictability. On top of this, we develop a new algorithm, which generates independent power maps to meet the spatial rank requirement and can also automatically select the order of the resulting thermal models for the given error bounds [C15, C16].

We are also working on the composite/composable thermal modeling techniques, in which each thermal model can be connected electronically based on their physical connections in the large structure system to build a large thermal system for fast thermal validations. We will start from the accurate finite difference or finite element methods and build the compact thermal models with novel reduction techniques [C14].

Recently we proposed a new method, called FRETEP, to accurately estimate and predict the full-chip temperature at runtime under more practical conditions where we have inaccurate thermal model, less accurate power estimations and limited number of on-chip physical thermal sensors. First, we propose a new thermal sensor based error compensation method to correct the errors due to the inaccuracies in thermal model and power estimations. Second, we raise a new correlation based method for error compensation estimation with limited number of thermal sensors. Third, we optimize the compact modeling technique and integrate it into the error compensation process in order to perform the thermal estimation with error compensation at runtime. Last but not least, to enable accurate temperature prediction for the emerging predictive thermal management, we design a full-chip thermal prediction framework employing time series prediction method [C17]. To address the power estimation aspect of this project, our group also made a number of contributions. First we proposed a new unit power estimation method based on the total power and access counts in the modern single and multi-core microprocessors [C3].

Another important contribution we made is the statistical leakage power analysis. One profound change in the chip design business is that engineers can't put the design precisely into the silicon chips. The so-called manufacture process variations start to play a big role and their influence on the chip's performance, yield and reliability becomes significant. Leakage power is specially sensitive to the process variations as the leakage power change exponentially with channel lengths and threshold voltages, to consider process vitiations specially in the presence of spatial correlations among the process variables, non-linear (quadratic) time complexity is required to compute the important statistical information (mean, variance). We also proposed to address this efficiency problem first by variable reductions via PCA (principal component analysis) and orthogonal polynomial representations [J5, C9]. This approach works quite well if the spatial correlations are strong. To address this outstanding issue, we further proposed a linear time complexity algorithm, for the first time, using the virtual grid techniques (originally proposed by IBM for statistical timing analysis) [ C12,C13] . The resulting algorithm has linear time complexity for both weak and strong correlations and has very good accuracy and many order of magnitudes faster than the state-of-the-art methods.

In addition to the thermal estimation problem, we also addressed the thermal-aware design to improve the reliability of on chip caches in the high-performance microprocessor design in the past [C4].

Highlights

Invited Presentations by Dr. Sheldon Tan

Computer Science and Engineering Colloquium, UCR, “Architecture-level thermal and power modeling and simulation for high performance microprocessor”, May 21, 2007.
Bejing Normal University, Beijing, China,” Architecture-level power modeling and thermal estimation for high performance microprocessor designs”, July 9, 2007.
Tsinghua University, Beijing, China, “Architecture-level power modeling and thermal estimation for high performance microprocessor designs”, July 18, 2007.
Electrical Engineering Colloquium, UCR, “Architecture level power, thermal modeling, and reliable cache design for high-performance multi-core microprocessors”, Oct. 22, 2007.
Fudan Univ. Shanghai, China, “Architecture-level Thermal Modeling and Simulation for Chip-Multiprocessor Designs”, July. 10, 2008.
Intel Corporation, Corporation Technology Group, Hillsboro, OR, “Architecture-level Thermal Modeling and Simulation for Multi-Core Architecture Design”, Oct. 17, 2008.
International Workshop on Emerging Circuits and Systems (IWECS’09), Shanghai, China, “Chip-Level parameterized thermal modeling for multi-core microprocessor design”, July 6, 2009.
2nd Nanoelectronics and Advanced Design Seminar at INAOE (Institute National Astrophysics, Optical and Electrics) at Puebla, Mexico , “Architecture-level Thermal Modeling and Simulation for Multi-Core Chip Design”, May 21, 2010.
International Workshop on Emerging Circuits and Systems (IWECS’10), Hefei, China, “Composable Thermal Modeling for Multicore Microprocessor Design”, August 5, 2010.
University of Electronic Science and Technology of China (UESTC), Chengdu, China, “Thermal Modeling and Estimation for Multi-Core Microprocessor Design”, August 10, 2010.
Intel Corp. Chandler, AZ, ATTD Group, “Chip-Level Thermal Modeling and Characterizations for Single and Multi Core Processor Designs”, Sept. 13, 2010.

Software Package Release

The Thermal Moment Matching analysis tool, TMM (in github with source codes), which can perform fast transient thermal analysis in almost linear time complexity.

ThermPOF (in github with source codes) , which is the matrix-pencil based thermal behavioral modeling technique.

ThermSID (in github with source codes), which is subspace identification based thermal behavioral modeling technique.

ThermalSubCP (in github with source codes), which perform the thermal modeling considering realistic power maps.

Relevant Publications

Journal publications

J1. P. Liu, H. Li, L. Jin, W. Wu, S. X.-D. Tan and J. Yang, “Fast thermal simulation for runtime temperature tracking and management”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and System, vol. 25, no. 12, pp. 2882-2893, 2006.
J2. W. Wu, L. Jin, , J. Yang, P. Liu and S. X.-D. Tan, “Efficient power modeling and software thermal sensing for runtime temperature monitoring ”, ACM Transaction on Design Automation of Electronic Systems (TODAES), vol. 12, no. 3, August, 2007.
J3. S. X.-D. Tan, P. Liu, L. Jiang, W. Wu, M. Tirumala, “A fast architecture-level thermal analysis method for runtime thermal regulation”, ASP Journal of Low Power Electronics (JOLPE), vol. 4, no. 4, August, pp.139-148, 2008.
J4. D. Li, S. X.-D. Tan, E. H. Pacheco, M. Tirumala, “Architecture-level thermal characterization for multi-core microprocessors”, IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), vol. 17, no. 10, pp. 1495-1507, October, 2009.
J5. R. Shen, S. X.-D. Tan, N. Mi and Y. Cai, “Statistical modeling and analysis of chip-level leakage power by spectral stochastic method”, Integration, The VLSI Journal, vol. 43, no. 1, pp. 156-165, January 2010. (online permanent DOI Link)
J6. D. Li, S. X.-D. Tan, E. H. Pacheco, M. Tirumala, “Parameterized architecture-level thermal modeling for multi-core microprocessors”, ACM Transaction on Design Automation of Electronic Systems (TODAES), vol. 15, no. 2, pp.1-22, February 2010 (one of top 10 downloaded ACM TODAES Articles published in 2010).
J7. T. Eguia, S. X.-D. Tan, R. Shen, D. Li, E. H. Pacheco, M. Tirumala, L. Wang, “General parameterized thermal modeling for high-performance microprocessor design”, IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), Vol. 20, No. 2, pp.221-224, Feb. 2012. 10.1109/TVLSI.2010.2098054.
J8 H. Wang, S. X.-D. Tan, D. Li, A. Gupta, Y. Yuan, “Composable Thermal Modeling and Simulation for Architecture-Level Thermal Designs of Multi-core Microprocessors”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 18, no. 2, March 2013.
J9 Z. Liu, S. X.-D. Tan, H. Wang, Y. Hua, and A. Gupta, “Compact thermal modeling for packaged microprocessor design with practical power maps”, Integration, The VLSI Journal, vol. 47, no. 1, January 2014. (One of the most downloaded papers in 2014 after its publication, 178 downloads in 3 months) see: http://www.journals.elsevier.com/integration-the-vlsi-journal/most-downloaded-articles/Online access: http://www.sciencedirect.com/science/article/pii/S0167926013000412

Conference publications

C1 H. Li, P. Liu, Z. Qi, L. Jin, W. Wu, S. X.-D. Tan, and J. Yang, “Efficient thermal simulation for run-time temperature tracking and management”, in Proc. Int. Conf. Computer Design (ICCD), pp.130-133, San Jose, CA 2005.
C2 P. Liu, Z. Qi, H. Li, L. Jin, W. Wu, S. X.-D. Tan and J. Yang, “Fast thermal simulation for architecture level dynamic thermal management”, Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), pp.639-644, San Jose, CA, Nov. 2005.
C3 W. Wu, L. Jin, J. Yang, P. Liu and S. X.-D. Tan “A systematic method for functional unit power estimation in microprocessors”, Proc. IEEE/ACM Design Automation Conference (DAC’06), pp.554-557, CA, 2006.
C4 W. Wu, J. Yang, S. X.-D. Tan, S.-L. Lu, “Improving the reliability of on-chip caches under process variations”, in Proc. Int. Conf. Computer Design (ICCD), Lake Tahoe, pp. 325-332, CA 2007. Best Paper Award (<2%).
C5 D. Li, S. X-.D. Tan, and M. Tirumala, “Architecture-level thermal behavioral modeling for quad-core microprocessors”, IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), pp. 22-27, San Jose, CA, Sept., 2007.
C6 D. Li, S. X.-.D. Tan, and M. Tirumala, “Architecture-level thermal behavioral characterization for multi-core microprocessors”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’08), pp.456-461, Seoul, Korea, Jan. 2008.
C7 P. Liu, S. X.-D. Tan, W. Wu and M. Tirumala, “FEKIS: A fast architecture-level thermal analyzer for online thermal regulation”, Proc. IEEE/ACM International Great Lakes Symposium on VLSI (GLSVLSI’08), pp. 411-416, Orlando, 2008.
C8 D. Li, S. X.-.D. Tan, E. H. Pacheco, M. Tirumala, “Parameterized transient thermal behavioral modeling for chip multiprocessors”, Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), pp. 611-617, San Jose, CA, Nov. 2008.
C9 R. Shen, N. Mi, S. X.-D. Tan, Y. Cai, X. Hong, “Statistical modeling and analysis of chip-level leakage power by spectral stochastic method”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’09), pp. 161-166, Yokohama, Japan, Jan. 2009.
C10 T. Eguia, S. X.-D. Tan, E. H. Pacheco, M. Tirumala, “Architecture level thermal modeling for multi-core systems using subspace system method”, in Proc. International Conference on ASIC (ASICON’09), pp. 714-717, Changsha, China, Oct. 2009. (Invited).
C11 T. Eguia, S. X.-D. Tan, R. Shen, E. H. Pacheco, M. Tirumala, “General behavioral thermal modeling and characterization for multi-core microprocessor design”, Proc. Design, Automation and Test in Europe (DATE'10), Dresden, Germany, pp.1136-1141, March 2010.
C12 R. Shen, S. X.-D. Tan, J. Xiong, “A linear statistical analysis for full-chip leakage power with spatial correlation”, Proc. IEEE/ACM International Great Lakes Symposium on VLSI (GLSVLSI’10), pp.27-232, Providence, RI, May, 2010.
C13 R. Shen, S. X.-D. Tan, J. Xiong, “A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation”, Proc. IEEE/ACM Design Automation Conference (DAC’10), pp.481-486, Anaheim, CA, 2010.
C14 H. Wang, D. Li, S. X.-D. Tan, M. Tirumala and A. X. Gupta “Composable thermal modeling and characterization for fast temperature estimation”, Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), Oct, Austin, TX, 2010.
C15 Z. Liu, S. X.-D. Tan, H. Wang, R. Quintanilla and A. Gupta, “Compact thermal modeling for package design with practical power maps”, 1st International IEEE Workshop on Thermal Modeling and Management: Chips to Data Centers (TEMM), Orlando, FL, July, 2011.
C16 Z Liu and S. X.-D. Tan, Rafael Quintanilla and Ashish Gupta, “Compact behavioral thermal modeling for microprocessor design with spatially correlated power inputs”, TECHCON , Austin, 2011.
C17 H. Wang, S. X.-D. Tan, G. Liao, R. Quintanilla and A. Gupta, “Full-chip runtime error-tolerant thermal estimation and prediction for practical thermal management”, Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2011.
C18 H. Wang, S. X.-D. Tan, X. Liu, A. Gupta, “Runtime power estimator calibration for high-performance microprocessors”, Proc. Design, Automation and Test in Europe (DATE'12), pp.352-357, Dresden, Germany, March 2012.
C19 Z. Liu, S. X.-D. Tan, H. Wang, Y. Hua, and A. Gupta, “Compact nonlinear thermal modeling of packaged microprocessors”, TECHCON’2012 , Austin, TX, Sept. 2012.
C20 S. Xu, Y. Hua, and S. X.-D. Tan, “Thermal modeling and temperature prediction using least square model averaging with model screening”, TECHCON’2012 , Austin, TX, Sept. 2012.
C21 Z. Liu, S. X.-D. Tan, H. Wang, A. Gupta, and S. Swarup , “Compact nonlinear thermal modeling of packaged integrated systems”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’13), pp. 157-162, Yokohama, Japan, Jan. 2013
C22 H. Wang, S. X.-D. Tan, S. Swarup, and X. Liu, “A power-driven thermal sensor placement algorithm for dynamic thermal management”, Proc. Design, Automation and Test in Europe (DATE'13), pp.1215-1220, Grenoble, France, March 2013.

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finished

Statistical Characterization and Simulation of VLSI Circuits Considering Process Variations

jbradfield — Thu, 01 Aug 2019 22:27:08 +0000

Statistical Characterization and Simulation of VLSI Circuits Considering Process Variations jbradfield Thu, 08/01/2019 - 15:27 More Project August 01, 2011

Principle Investigators

Dr. Sheldon Tan (PI)

Collaborators

Dr. Yici Cai, Tsinghua University, China
Dr. Hao Yu, NTU, Singapore
Dr. Jinjun Xiong, IBM T. J. Watson Research Center, USA
Dr. Chandu Visweswariah, IBM, USA

Graduate Students

Yue Zhao
Ruijing Shen,
Duo Li,
Zhigang Hao,
Ning Mi

Funding supports

National Science Foundation, “SHF: Small: Variational and Bound Performance Analysis of Nanometer Mixed-Signal/Analog Circuits”, (CCF-1116882), 9/1/2011-8/30/2014, PI: Sheldon Tan

National Science Foundation, “IRES: Development of Global Scientists and Engineers by Collaborative Research on Variation-Aware Nanometer IC Design”, (OISE-1130402), 9/1/2011-8/30/2014, PI: Sheldon Tan, co-PI: Yici Cai

National Science Foundation, “US-Singapore Planning Visit: Collaborative Research on Design and Verification of 60Ghz RF/MM Integrated Circuits”, (OISE-1051797), 4/1/2011-3/30/2013, PI: Sheldon Tan, co-PI: Hao Yu.

2011 UC MEXUS-CONACYT Collaborative Research Grants, “Symbolic and Statistical Modeling and Analysis Techniques for Analog/Mixed-Signal Nanometer Integrated Circuits”, 2011-2013 academic year , 9/1/2011-2/31/2013, PI: Sheldon Tan

2009 UC MEXUS-CONACYT Collaborative Research Grant, “Symbolic modeling and reduction for analog/RF circuits and on-chip interconnect”, Aug 2009 to Jan 2011, PI, co-PI: Dr. Esteban Tlelo-Cuautle.

National Science Foundation, “IRES: Development of Global Scientists by Research Collaborations on Simulation and Optimization of Nanometer Integrated Systems”, (OISE-0623038), 9/1/2006-8/30/2009, PI: Sheldon Tan, co-PI: Yici Cai

National Science Foundation, “CAREER: Career Development Plan: Behavioral Modeling, Simulation and Optimization for Mixed-Signal System in a Chip”, (CCF-0448534, a number of REU supplements), 6/1/2005-5/31/2011. PI: Sheldon Tan.

Project Descriptions

Background

As VLSI technology scales into the nanometer regime, chip design engineering face several challenges in maintaining historical rates of performance improvement and capacity increase with CMOS technologies. One profound change in the chip design business is that engineers can't put the design precisely into the silicon chips. Chip performance, manufacture yield and lifetime become unpredictable at the design stage. Chip performance, manufacture yield and lifetime can't be determined accurately at the design stage. The main culprit is that many chip parameters -- such as oxide thickness due to chemical and mechanical polish (CMP) and impurity density from doping fluctuations -- can't be determined precisely, and thus are unpredictable. The so-called manufacture process variations start to play a big role and their influence on the chip's performance, yield and reliability becomes significant.

As a result, how to efficiently and accurately assess the impacts of the process variations of interconnects in the various physical design steps are critical for fast design closure, yield improvement, cost reduction of VLSI design and fabrication processes. The design methodologies and design tools from system level down to the physical levels have to embrace variability impacts on the VLSI chips, which calls for statistical/stochastic based approaches for designing 90nm and beyond VLSI systems.

In this regard, it is imperative to develop new design methodologies to consider the impacts of various process and environmental uncertainties and elevated temperature on chip performance. Variational impacts and thermal constraints have to be incorporated into every steps of design process to ensure the reliable chips and profitable manufacture yields. The design methodologies and design tools from system level down to the physical levels have to consider variability and thermal impacts on the chip performance, which calls for new statistical and thermal-aware optimization approaches for designing nanometer VLSI systems. The PI’s group at UCR has been working on statistical modeling and simulation of VLSI systems since 2006 and has made a number of contributions in this field. We have proposed statistical on-chip power grid analysis approaches based spectral stochastic method[ J1,J2,J5,C1,C3,C5,C7,C10], stochastic model order reduction methods [C2C4], stochastic capacitance and inductance extraction techniques [J3,C8, C15], statistical leakage and power (total and dynamic power) analysis techniques [J4,C11,C13,C14,C16,C17], performance bound and mismatch analysis of analog and mixed-signal circuits [C9, C12,C18], statistical timing analysis [J6,C9] and variational impact analysis on the on-chip cache design [C6]. A book summarized our works in a systemic way will be published by Springer in 2012 [B1].

This proposal tries to addresses the fundamental and emerging challenges in performance analysis under process parameter variability for analog/mixed-signal and VLSI circuits. The main goal of this program is to develop novel and efficient non-Monte-Carlo techniques for worst-case and statistical analysis of analog/mixed-signal circuits.

Goals of the project

Specifically, we seek the following goals for the project

Development of novel worst-case analysis methods for analog/mixed-signal circuits based on graph-based symbolic analysis, affine-like interval arithmetic and Kharitonov’s functions. The new method will first build variational transfer functions from linearized analog circuit by determinant decision diagram (DDD) based symbolic analysis and affine-like interval arithmetic. Then the performance bounds will be computed by Kharitonov’s functions from the variational transfer functions. We will investigate more conservative affine-like interval arithmetic to reduce conservation. We will investigate the performance bounds in the time domains given frequency domain bounds.
Development of fast non-Monte-Carlo statistical analysis methods to calculate mismatch due to process variations. We model the problem as solving nonlinear stochastic differential-algebra-equations. Nonlinear stochastic methods (Galerkin or collocation methods) and trajectory-piecewise-linear macromodeling method with incremental subspace aggregation will be applied to solve the resulting problems.
Fast Monto-Carlo or other statisitical methods for rate event (high sigma) and more variables (high dimentional) statistiical analysis.

Invited Presentations by Dr. Sheldon Tan

IBM Watson Research Center, Yorktown Height, NY, “Variational Analysis for Large Power Delivery Networks and Full-Chip Leakage Powers of Nanometer VLSI Systems”, Nov. 5, 2008.
Shanghai Jiao Tong University, School of Microelectronics, Shanghai, China, “Variational Analysis of Full-Chip Leakage Power in Nanometer VLSI Systems”, June 16, 2009.
Xi'an Institute of Post & Telecommunications, Dept of Computer Science, Xi'an, Shaanxi Province, China, “Variational Analysis of Clock Networks Considering Environmental Uncertainty”, July 8, 2009.
Xi’an Jiao Tong University, Dept of Electrical Engineering, Xi’an, Shaanxi Province, China, “Variational Analysis of Clock Networks Considering Environmental Uncertainty”, July 10, 2009.
Fudan Univ. Shanghai, China, “Statistical Analysis of Full-Chip Leakage Power in Nanometer VLSI Systems”, July. 23, 2010.
Shanghai Jiao Tong University, School of Microelectronics, Shanghai, China, “Performance bound analysis of analog circuits considering process variation”, May 30, 2011.
The University of Hong Kong, Department of Electrical and Electronic Engineering, Hong Kong, China, “Graph-based Parallel and Statistical Analysis of Analog Circuits Based on GPU Platforms”, Hong Kong, Aug. 23, 2011.
The EDA workshop, Department of Electrical Engineering, National Taiwan University, Taiwan, “Performance Bound Analysis for Analog Circuits Under Process Variations”, Sept 10, 2011.
International Workshop on Emerging Circuits and Systems (IWECS’12), Shanghai Jiao Tong University, Shanghai, China, “Parallel Computing and Simulation for VLSI systems”, Aug. 9, 2012.
INAOE (Institute National Astrophysics, Optical and Electrics), Department of Electrical Engineering, Puebla, Mexico , “Fast GPU-accelerated Sparse Matrix-Vector Multiplication”, May 3, 2013.

Software package releases

Relevant Publications

Book and book chapter publications

B1. Ruijing Shen, Sheldon X.-D. Tan and Hao Yu, Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs, Springer Publisher, March 2012, ISBN-10: 1461407877.
B2. Sheldon X.-D. Tan, Ruijing Shen, “Chip-Level Statistical Leakage Modeling and Analysis”, Chapter in Recent Advancements in Modeling of Semiconductor Processes, Circuits and Chip-Level Interactions, Rasit Onur Topaloglu, and Peng Li (Editors), Bentham Publishing (www.ebook-engineering.org), 2010 (in press).
B3. Xue-Xin Liu, Hao Yu, Hai Wang, Sheldon X.-D. Tan, “Analog mismatch analysis by stochastic nonlinear macromodeling”, Chapter in “Analog Circuits: Applications, Design and Performances”, E. Tlelo-Cuautle (Editor), NOVA Science Publishers Inc. ISBN: 978-1-61324-355-8.
B4. Guoyong Shi, Sheldon X.-D. Tan, Esteban Tlelo-Cuautle, “Advanced Symbolic Analysis for VLSI Systems -- Methods and Applications”, Springer Publisher, 2014, ISBN 978-1-4939-1103-5

Journal publications

J1. N. Mi, J. Fan, S. X.-D. Tan, Y. Cai and X. Hong, “Statistical analysis of on-chip power delivery networks considering lognormal leakage current variations with spatial correlations”, IEEE Transaction on Circuit and System I (TCAS-I), vol. 55, no. 7, pp.2064-2075, August, 2008.
J2. N. Mi, S. X.-D. Tan, Y. Cai and X. Hong, “Fast variational analysis of on-chip power grids by stochastic extended Krylov subspace method”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 11, pp. 1996-2006, 2008.
J3. R. Shen, S. X.-D. Tan, J. Cui, W. Yu, Y. Cai and G. Chen, “Variational capacitance extraction and modeling based on orthogonal polynomial method”, IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), vol.18, no.11, pp1556-1565, 2010.
J4. R. Shen, S. X.-D. Tan, N. Mi and Y. Cai, “Statistical modeling and analysis of chip-level leakage power by spectral stochastic method”, Integration, The VLSI Journal, vol. 43, no. 1, pp. 156-165, January 2010. (online permanent DOI Link)
J5. D. Li, S. X.-D. Tan, “Statistical analysis of large on-chip power grid networks by variational reduction scheme”, Integration, The VLSI Journal, vol. 43, no. 2, pp.167-175, April, 2010.
J6. H. Wang, H. Yu, S. X.-D. Tan, “Fast timing analysis of clock networks considering environmental uncertainty”, Integration, The VLSI Journal, online available at http://dx.doi.org/10.1016/j.vlsi.2011.03.001
J7. Z. Hao, S. X.-D. Tan, E. Tlelo-Cuautle, J. Relles, C. Hu, W. Yu, Y. Cai and G. Shi, “Statistical extraction and modeling of inductance considering spatial correlation”, Analog Integr Circ Sig Process, July 2011. DOI: 10.1007/s10470-011-9720-8.
J8. F. Gong, X. Liu, H. Yu, S. X.-D. Tan, J. Ren and L. He, "A fast non-Monte-Carlo yield analysis and optimization by stochastic orthogonal polynomials", ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 17, no.1, pp10:1-10:23, January 2012. 10.1145/2071356.2071366
J9. Z. Hao, S. X.-D. Tan, G. Shi, “Statistical full-chip total power estimation considering spatially correlated process variations”, Integration, The VLSI Journal, Vol. 73, no. 1, 2012. doi:10.1016/j.vlsi.2011.12.004
J10. R. Shen, S. X.-D. Tan, H. Wang, J. Xiong, “Fast statistical full-chip leakage analysis for nanometer VLSI systems”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 17, no. 4, pp.51:1--51:19, Sept. 2012. 10.1145/2348839.2348855
J11. Z. Hao, G. Shi, S. X.-D. Tan, E. Tlelo-Cuautle, “Symbolic moment computation for statistical analysis of large interconnect networks”, IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), vol. 21, no. 5, pp. 944-957, May 2013
J12. X. Liu, S. X.-D. Tan, A. Palma-Rodriguez, E. Tlelo-Cuautle, G. Shi, and Y. Cai, “Performance bound analysis of analog circuits in frequency and time domain considering process variations”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 19, no. 6, Dec. 2013.

Conference publications

C1 N. Mi, J. Fan, S. X.-D. Tan, “Statistical analysis of power grid networks considering lognormal leakage current variations with spatial correlation”, in Proc. Int. Conf. Computer Design (ICCD), pp.56-62, San Jose, CA 2006.
C2 J. Fan, N. Mi, S. X.-D. Tan, “Variational compact modeling and simulation for linear dynamic systems”, IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), pp.17-22, San Jose, CA, Sept., 2006.
C3 N. Mi, J. Fan, S. X.-D. Tan, “Simulation of power grid networks considering wires and lognormal leakage current variations”, IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), pp.73-78, San Jose, CA, Sept., 2006.
C4 J. Fan, N. Mi, S. X.-D. Tan, Y. Cai and X. Hong, “Statistical model order reduction for interconnect circuits considering spatial correlations”, Proc. Design, Automation and Test in Europe (DATE'07), pp. 1508-1513, Nice, France, April 2007.
C5 N. Mi, S. X.-D. Tan, P. Liu, J. Cui, Y. Cai and X. Hong, “Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks”, Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), pp.48-53, San Jose, CA, Nov. 2007.
C6 W. Wu, J. Yang, S. X.-D. Tan, S.-L. Lu, “Improving the reliability of on-chip caches under process variations”, in Proc. Int. Conf. Computer Design (ICCD), Lake Tahoe, pp. 325-332, CA 2007. Best Paper Award (<2%).
C7 X. Yuan, J. Fan, B. Liu, S. X.-D. Tan, “Stochastic based extended Krylov subspace method for power/ground network analysis”, in Proc. 7th International Conference on ASIC (ASICON’07), Guilin, China, Oct. 2007. (Invited).
C8 J. Cui, G. Chen, R. Shen, S. X.-D. Tan, W. Yu, J. Tong, “Variational capacitance modeling using orthogonal polynomial method”, Proc. IEEE/ACM International Great Lakes Symposium on VLSI (GLSVLSI’08), pp. 23-28, Orlando, 2008.
C9 H. Wang, H. Yu, S. X.-D. Tan, “Fast analysis of non-tree clock network considering environmental uncertainty by parameterized and incremental macromodeling”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’09), pp. 379-384, Yokohama, Japan, Jan. 2009.
C10 D. Li, S. X.-.D. Tan, G. Chen and X. Zeng, “Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization method” Proc. Asia South Pacific Design Automation Conference (ASP-DAC’09), pp. 272-277, Yokohama, Japan, Jan. 2009.
C11 R. Shen, N. Mi, S. X.-D. Tan, Y. Cai, X. Hong, “Statistical modeling and analysis of chip-level leakage power by spectral stochastic method”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’09), pp. 161-166, Yokohama, Japan, Jan. 2009.
C12 H. Yu, X. Liu, H. Wang, S. X.-D. Tan, “A fast analog mismatch analysis by an incremental and stochastic trajectory piecewise linear macromodel”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’10), pp.211-216, Taipei, Taiwan, Jan. 2010.
C13 R. Shen, S. X.-D. Tan, J. Xiong, “A linear statistical analysis for full-chip leakage power with spatial correlation”, Proc. IEEE/ACM International Great Lakes Symposium on VLSI (GLSVLSI’10), pp.27-232, Providence, RI, May, 2010.
C14 R. Shen, S. X.-D. Tan, J. Xiong, “A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation”, Proc. IEEE/ACM Design Automation Conference (DAC’10), pp.481-486, Anaheim, CA, 2010.
C15 J. Relles, M. Ngan, E. Tlelo-Cuautle, S. X.-D. Tan, C. Hu, W. Yu and Y. Cai, “Statistical extraction and modeling of 3D inductance with spatial correlation”, IEEE International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD), Tunisia, October 5-6, 2010.
C16 Z. Hao, R. Shen, S. X.-D. Tan, B. Liu, G. Shi and Y. Cai, “Statistical full-chip dynamic power estimation considering spatial correlations”, Proc. Int. Symposium. on Quality Electronic Design (ISQED’11), San Jose, CA, pp677-782, March 2011.
C17 Z. Hao, S. X.-D. Tan, G. Shi, “An efficient statistical chip-level total power estimation method considering process variations with spatial correlation”, Proc. Int. Symposium. on Quality Electronic Design (ISQED’11), pp.671-676, San Jose, CA, March 2011.
C18 Z. Hao, S. X.-D. Tan, R. Shen, G. Shi, “Performance bound analysis of analog circuits considering process variations”, Proc. IEEE/ACM Design Automation Conference (DAC’11) , pp.310-315, San Diego, CA, June 2011.
C19 X. Liu, S. X.-D. Tan, Z. Hao, G. Shi, “Time-domain performance bound analysis of analog circuits considering process variations”, ”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’12), Sydney, Australia, pp.535-540, Jan. 2012.
C20 X. Liu, S. X.-D. Tan, and H. Wang, “Parallel statistical analysis of analog circuits by GPU-accelerated graph-based approach”, Proc. Design, Automation and Test in Europe (DATE'12), pp.852-857, Dresden, Germany, March 2012.
C21 R. Shen, S. X.-D. Tan and X. Liu, “A new voltage binning technique for yield improvement based on graph theory”, Proc. Int. Symposium on Quality Electronic Design (ISQED’12), San Jose, CA, March 2012.
C22 S. Rodriguez-Chavez , E. Tlelo-Cuautle, A. Palma-Rodriguez, S. X.-D. Tan, “Symbolic DDD-based tool for the computation of noise in CMOS analog circuits”, 8th International Caribbean Conf. on Devices, Circuits and Systems (ICCDCS), Playa del Carmen, Mexico, March 2012.
C23 A. Palma-Rodriguez, S. Rodriguez-Chavez , E. Tlelo-Cuautle, S. X.-D. Tan, “DDD-based symbolic sensitivity analysis of active filters”, 8th International Caribbean Conf. on Devices, Circuits and Systems (ICCDCS), Playa del Carmen, Mexico, March 2012.
C24 X. Liu, A. Palma-Rodriguez , S. Rodriguez-Chavez, S. X.-D. Tan, E. Tlelo-Cuautle, Y. Cai, “Performance bound and yield analysis for analog circuits under process variations”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’13), pp.761-766, Yokohama, Japan, Jan. 2013.
C25 T. Yu, S. X.-D. Tan, Y. Cai, and P. Tang, “Time-domain performance bound analysis for analog and interconnect circuits considering process variations”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’14), Singapore, Singapore, Jan. 2014.
C26 A. Zhang, G. Shi, S. X-.D. Tan, J. Cheng, “Simultaneous SNR and SNR-variation optimization for Sigma-Delta modulator design”, Int, Conf. Solid State and Integrated Circuit Technology (ICSICT’04), Guilin, China, Oct. 2014.
C27 Y. Zhu, S. X.-D. Tan, “GPU-accelerated parallel Monte Carlo analysis of analog circuits by hierarchical graph-based solver”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’15), Chiba, Japan, Jan. 2015.

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Parallel Computing and Simulation and of Nanometer VLSI Systems based on Multi/Many Core and GPU platforms

jbradfield — Thu, 01 Aug 2019 22:26:30 +0000

Parallel Computing and Simulation and of Nanometer VLSI Systems based on Multi/Many Core and GPU platforms jbradfield Thu, 08/01/2019 - 15:26 More Project August 01, 2010

Principle Investigators

Dr. Sheldon Tan (PI)

Collaborators

Dr. Yici Cai, Tsinghua University, China
Dr. Hao Yu, NTU, Singapore
Dr. Lifeng Wu, ProPlus Design Solutions Inc.

Graduate Students

Current graduate students

Kai He,
Hengyang Zhao

Graduate Students (gradudated)

Joseph Gordon (M.S.)
Xue-Xin Liu (Ph.D)

Funding support

We thank National Science Foundations for supports of this research work. Any opinions, findings, and conclusions or recommendations expressed in those materials below are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.

National Science Foundation, “CAREER: Career Development Plan: Behavioral Modeling, Simulation and Optimization for Mixed-Signal System in a Chip”, (CCF-0448534, a number of REU supplements), 6/1/2005-5/31/2011. PI: Sheldon Tan.

National Science Foundation, “US-Singapore Planning Visit: Collaborative Research on Design and Verification of 60Ghz RF/MM Integrated Circuits”, (OISE-1051797), 4/1/2011-3/30/2013, PI: Sheldon Tan, co-PI: Hao Yu.

National Science Foundation, “SHF: Small: GPU-Based Many-Core Parallel Simulation of Interconnect and High-Frequency Circuits”, (CCF-1017090), 9/1/2010-8/30/2013, PI: Sheldon Tan

Project Descriptions

Background

Modern computer architecture has shifted towards designs that employ multiple processor cores on a chip, so called multicore processor or chip-multiprocessors (CMP). The leap from single-core to multi-core technology has permanently altered the course of computing. CMP enables increased productivity, powerful energy-efficient performance, and breakthrough in parallel computing capability and scalability. We expect a continuing trend of increasing the number of cores on a die to maximize the performance/power efficiency of a single chip. The graphic processing unit (GPU) are one of the most powerful many-core computing systems in use. For instance, Nvidia GeForce GTX 280 chip has a peak performance of over 900 GFLOPS versus 12.8 GFLOPS for 3.2 Ghz Pentium IV CPU. In addition to the primary use of GPUs in accelerating graphics rendering operations, there has been considerable interests in exploiting GPUs for general purpose computation (GPGPU). The introduction of new parallel programming interfaces for general purpose computations, such as Computer Unified Device Architecture (CUDA), Stream SDK and OpenCL, have made GPUs powerful and attractive choice for developing high-performance numerical, scientific computation and solving practice engineering problems. However, programming on GPUs remains a challenging problem. The reason is that many modern GPUs exhibit complex memory organization with multiple low latency on-chip memories in addition to the off-chip memory. The access latencies and the optimal access patterns of each of the memories vary significantly, posing a significant challenge to develop techniques that optimally utilize the various memories to tolerate the latency and improve the memory thoughtful. The memory hierarchy along with the highly parallel execution model make application optimization difficult. The challenges increase many-fold when the application to be optimized and parallelized are memory-intensive operations such as Sparse Matrix-Vector multiplication (SpMV), which is the critical kernel for most analysis and simulation tasks for VLSI chip designs.

Simulation of VLSI chips at circuit level still remain the difficult tasks as more than half of the design time are spent on the verification tasks. The percentage is growing as the technologies scale down due to exploding growth of extracted parasitics and increasing operation frequencies in high performance microprocessors, radio-frequency (RF) and microwave/millimeter-wave (MM) integrated circuits (ICs). The staggering amount of design data generated during the chip design processes poses tremendous design and verification challenges.

In this project, we focus on the parallelization of simulation and analysis algorithms for VLSI systems such as global interconnects and high frequency RF/MM integrated circuits. VLSI simulations task typically are memory-intensive operations as they needs to analyze and transform huge amount of design data. As the GPUs are becoming viable and commodity high-performance computing platforms, accelerating those critical simulation tasks on GPUs will bring tremendous and immediate benefits for the design communities.

To further promote the research, the PI also proposed and taught a new graduate level course, EE-CS 217: GPU Architecture and Parallel Programming (http://www.ee.ucr.edu/~stan/courses/eecs217/eecs217_home.htm) to promote the GPU-related research. The PI taught the course in the Winter 2011 and Winter 2012 at UCR and the course was received by UCR graduate students from both EE and CS departments. In addition, the PI also established UCR CUDA Teaching Centers (2010-2011) sponsored by Nvidia Corporation, CA, to advancing the state of parallel education using CUDA C/C++. CUDA Teaching Center comes with equipment donations, funding support for course development, course material assistance and software license from Nvidia Corporation. Nivdia also provide partial TA supports for the proposed EE-CS217 course as part of CUDA Teaching Center program. The PI used the donation to build CUDA teaching lab at UCR so that students perform the labs for the EE217 course. See http://www.marketwire.com/press-release/NVIDIA-Names-20-New-CUDA-Research-and-Training-Centers-in-Seven-Nations-NASDAQ-NVDA-1372887.htm

The PI’s group (together with our collaborators) have developed several parallel simulation techniques based on multi-core and GPU platforms in the past:

GPU friendly fast analysis for structured on-chip power grid networks

Power integration verification of on-chip power grid networks are critical for design sign-off as aggressive scaling of supply voltages and shrinking design margins. We proposed a novel simulation algorithm for large scale structured power grid networks. The new method formulates the traditional linear system as a special two-dimension Poisson equation and solves it using an analytical expressions based on FFT technique. The computation complexity of the new algorithm is O(NlgN), which is much smaller than the traditional solver’s complexity O(N^1.5) for sparse matrices, such as the SuperLU solver and the PCG solver. Also, due to the special formulation, graphic process unit (GPU) can be explored to further speed up the algorithm. Initial results show that the new algorithm is stable and can achieve 100X speed up on GPU over the widely used SuperLU solver with very little memory footprint. [C1]

Parallel shooting-based method for RF circuits based on GPU platforms

The recent multi/many-core CPUs or GPUs have provided an ideal parallel computing platform to accelerate the time-consuming analysis of radio-frequency/millimeter-wave (RF/ MM) integrated circuit (IC). In this period, we have developed a structured shooting algorithm that can fully take advantage of parallelism in periodic steady state (PSS) analysis for RF and MM ICs. Utilizing periodic structure of the state matrix of RF/ MM-IC simulation, a cyclic-block-structured shooting-Newton method has been parallelized and mapped onto recent GPU platforms. We developed the formulation of the parallel cyclic-block-structured shooting-Newton algorithm, called “periodic Arnoldi shooting” method. Then we will present its parallel implementation details on GPU. Results from several industrial examples show that the structured parallel shooting-Newton method on Tesla's GPU can lead to speedups of more than 20 X compared to the state-of-the-art implicit GMRES methods under the same accuracy on the CPU. The initial results were published in [C2]

Parallel symbolic analysis techniques for analog and mixed-signal circuit

Graph-based symbolic technique is a viable tool for calculating the behavior or the characterization of an analog circuit. Traditional symbolic analysis tools typically are used to calculate the behavior or the characteristic of a circuit in terms of symbolic parameters. The introduction of determinant decision diagrams (DDD) (by the PI and his PhD advisor) based symbolic analysis technique allows exact symbolic analysis of much larger analog circuits than all the other existing approaches. In this period, the PI’s group proposed a new parallel analysis method for large analog circuits using determinant decision diagram (DDD) based graph technique. DDD-based symbolic analysis technique enables exact symbolic analysis of vary large analog circuits. Once the circuit small-signal characteristics are presented by DDDs, evaluation of DDDs will give exact numerical values. In this paper, we develop efficient parallel DDD evaluation techniques based on general purpose GPU (GPGPU) computing platform to explore the parallelism of DDD structures. We propose two parallelization algorithms and their performance are compared. Initial results show that the new evaluation algorithm can achieve about one to two order of magnitudes speedup over the serial CPU based evaluations on some large analog circuits. [C3,B1]. The statistical analog variational analysis based on DDD structure has been proposed recently [C5]. (4) A GPU-Accelerated Envelope-Following Method for Switching Power Converter Simulation We proposed a new envelope-following parallel transient analysis method for the general switching power converters. The new method first exploits the parallelisim in the envelope-following method and parallelize the Newton update solving part, which is the most computational expensive, in GPU platforms to boost the simulation performance. To further speed up the iterative GMRES solving for Newton update equation in the envelope-following method, we apply the matrix-free Krylov basis generation technique, which was previously used for RF simulation. Last, the new method also applies more robust Gear-2 integration to compute the sensitivity matrix instead of traditional integration methods. Experimental results from several integrated on-chip power converters show that the proposed GPU envelope-following algorithm leads to about 10X speedup compared to its CPU counterpart, and 100X faster than the traditional envelop-following methods while still keeps the similar accuracy [C4].

A GPU-accelerated general minimum residual iterative solver (GRMES) has ben developed (see software download below) and has been used for thermal analysis with advanced cooling techniques [C6].

Invited Presentations by Dr. Sheldon Tan

College of Engineering Seminar (CUDA Talk), UC Riverside, CA “Parallel computing method for on-chip power grid analysis based on the multi-core computing platforms”, June 2, 2009.

International Workshop on Emerging Circuits and Systems (IWECS’11), Hangzhou, Zhejiang Provence, China, “Graph-based Parallel and Statistical Analysis of Large Analog Circuits Based on GPU Platforms", August 4, 2011.

The University of Hong Kong, Department of Electrical and Electronic Engineering, Hong Kong, China, “Graph-based Parallel and Statistical Analysis of Analog Circuits Based on GPU Platforms”, Hong Kong, Aug. 23, 2011.

Shanghai Jiaotong University, School of Microelectronics, Shanghai, China, “Graph-based Parallel and Statistical Analysis of Analog Circuits on GPU Platforms”, April 26, 2012

International Workshop on Emerging Circuits and Systems (IWECS’12), Shanghai Jiao Tong University, Shanghai, China, “Parallel Computing and Simulation for VLSI systems”, Aug. 9, 2012.

INAOE (Institute National Astrophysics, Optical and Electrics), Department of Electrical Engineering, Puebla, Mexico , “Fast GPU-accelerated sparse matrix-vector multiplication (SpMV)”, May 3, 2013.

Software Download

GLU Solver --- GPU-enabled parallel LU factorization solver package

GPU-GMRES (in github with sources codes and examples) -- Parallel GMRES (Generalized Minimal Residual) linear solver on GPU platforms for both RLC and thermal circuits.

Relevant Publications

Book or book chapters

B1. Sheldon X.-D. Tan, Xue-Xin Liu and Eric Mlinar, and Esteban Tlelo-Cuautle, “Parallel symbolic analysis of large analog circuits on GPU platforms”, Chapter in "VLSI Design", Esteban Tlelo-Cuautle and Sheldon X.-D. Tan (Editors), INTECH (www.intechweb.org), ISBN 978-953-307-884-7, January, 2012.
B2. Sheldon X.-D. Tan, Xue-Xin Liu and Eric Mlinar, and Esteban Tlelo-Cuautle, “Parallel symbolic analysis of large analog circuits on GPU platforms”, Chapter 6 in "VLSI Design", Esteban Tlelo-Cuautle and Sheldon X.-D. Tan (Editors), INTECH (www.intechweb.org), ISBN 978-953-307-884-7, January, 2012.
B3. X.-X. Liu, S. X.-D. Tan, H. Wang, and H. Yu, “GPU-accelerated envelope-following method”, Chapter 17 in “Designing Scientific Applications on GPU”, Raphael Couturier (Editor), CRC Press /Taylor & Francis Group, Nov. 2013. ISBN 9781466571648
B4. Guoyong Shi, Sheldon X.-D. Tan, Esteban Tlelo-Cuautle, “Advanced Symbolic Analysis for VLSI Systems -- Methods and Applications”, Springer Publisher, 2014, ISBN 978-1-4939-1103-5

Journal publications

J1. X. Liu, S. X.-D. Tan, H. Yu, “A GPU-accelerated parallel shooting algorithm for analysis of radio frequency and microwave integrated circuits”, IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), vol. 23, no. 3, March 2015.http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6777551
J2. X. Liu, K. Zhai, Z. Liu, K. He, S. X.-D. Tan, and W. Yu, “Parallel thermal analysis of 3D integrated circuits with liquid cooling on CPU-GPU platforms”, IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), vol. 23, no. 3, pp. 575-579, March 2015.
J3 K. He, S. X.-D. Tan, H. Wang and G. Shi, “GPU-accelerated parallel sparse LU factorization method for fast circuit analysis”, IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), (in press).

Conference publications

C1. J. Shi, Y. Cai, W. Hou, L. Ma, S. X.-D. Tan, P.-H. Ho and X. Wang, “GPU friendly fast Poisson solver for structured power grid network analysis”, Proc. IEEE/ACM Design Automation Conference (DAC’09), pp.178--183, San Francisco, CA, 2009. (Best Paper Award Nomination (7 out of 682 submissions, 1%))

C2. X. Liu, H. Yu, J. Relles, S. X-.D. Tan, “ A structured parallel periodic Arnoldi shooting algorithm for RF-PSS analysis based on GPU platforms”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’11), pp13-18, Yokohama, Japan, Jan. 2011.

C3. J. Lu, Z. Hao, S. X.-D. Tan, “Graph-based parallel analysis of large analog circuits based on GPU platforms”, ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU Workshop), April 2011.

C4. X. Liu, S. X.-D. Tan, H. Wang and H. Yu, “A GPU-accelerated envelope-following method for switching power converter simulation”, Proc. Design, Automation and Test in Europe (DATE'12), Dresden, Germany, March 2012.

C5. X. Liu, S. X.-D. Tan, and H. Wang, “Parallel statistical analysis of analog Circuits by GPU-accelerated Graph-based Approach”, Proc. Design, Automation and Test in Europe (DATE'12), Dresden, Germany, March 2012.

C6. X. Liu, Z. Liu, S. X.-D. Tan, J. Gordon, “Full-chip thermal analysis of 3D ICs with liquid cooling by GPU-accelerated GMRES method”, Proc. Int. Symposium on Quality Electronic Design (ISQED’12), San Jose, CA, March 2012.

C7. X. Liu, S. X.-D. Tan, Z. Liu, H. Wang, T. Xu, “Transient analysis of large linear dynamic networks on hybrid GPU-multicore platforms”, 10th IEEE International NEWCAS Conference, Montreal, Canada, pp. 173-176, June, 2012.

C8. X. Liu, H. Wang, and S. X.-D. Tan, “Parallel power grid analysis using preconditioned GMRES solvers on CPU-GPU platforms”, Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD’13), pp.561-568, San Jose, CA, Nov. 2013.

C9. K. He, S. X.-D. Tan, E. Tlelo-Cuautle, H. Wang and H. Tang, “A new segmentation-based GPU-accelerated sparse matrix-vector multiplication”, Proc. Int. Midwest Symposium on Circuits and Systems (MWSCAS’14), College Station, TX, August, 2014.

C10. Y. Zhu, S. X.-D. Tan, “GPU-accelerated parallel Monte Carlo analysis of analog circuits by hierarchical graph-based solver”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’15), Chiba, Japan, Jan. 2015.

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Compact Modeling, Reduction and Simulation of Interconnect Parasitic Circuits

jbradfield — Thu, 01 Aug 2019 22:23:43 +0000

Compact Modeling, Reduction and Simulation of Interconnect Parasitic Circuits jbradfield Thu, 08/01/2019 - 15:23 More Project August 01, 2008

Principle Investigator

Dr. Sheldon Tan (PI)

Graduate Students:

Hai Wang,
Boyuan Yan,
Duo Li,
Pu Liu

Funding supports

We appreciate the following funding agencies for their generous supports of this project.

National Science Foundation, "CAREER: Career Development Plan: Behavioral Modeling, Simulation and Optimization for Mixed-Signal System in a Chip", (CCF-0448534, CCF-0529754 and CCF-0731962, CCF- 0830304, for REU supplements), 6/1/2005-5/31/2011. PI: Sheldon Tan.
UC MICRO Program (via Cadence Design Systems Inc.) (#05-111), "Combined Multi-Input Multi-Output Model Order Reduction and Topology Reduction for High-Performance VLSI Systems", Sept. 2005 to Aug. 2006, PI: Sheldon Tan
UC MICRO Program (via Intel Corporation) (#07-105), "Compact Modeling Techniques for Inductively Coupled Interconnect Circuits", Sept. 2007 to Aug. 2008, PI: Sheldon Tan

Project Descriptions

As VLSI technology advances into the sub-100nm regime with increased operating frequency and decreased feature sizes, the nature of the VLSI design has changed significantly. One fundamental paradigm change is that parasitic interconnect effects dominate both the chip's performance and the design's complexity growth. Management of the design parasitic by circuit reduction techniques becomes impressive.

In this project, we investigate the compact modeling techniques of on-chip interconnects and general linear time invariant systems (LTI) because interconnect parasitics, which are modeled as linear RLCM circuits, are the dominant factors for complexity growth. Unchecked parasitics from on-chip interconnects and off-chip packaging will de-tune the performance of high-speed circuits in terms of slew rate, phase margin and bandwidth. Reduction of design complexity especially for the extracted high-order RLCM networks is crucial for reducing the explosive design productivity gap in the nanometer VLSI design and verification.

The PI and MSLAB at UC Riverside have many a number of contributions to this field in the past. In 2003, the PI proposed a new hierarchical model order reduction technique based on the Determinant Decision Diagram (DDD) symbolic analysis[J1]. The idea is to perform the hierarchical symbolic analysis (assume frequency variable s is the only parameter) and drive the truncated transfer functions. The approach was shown to be more accurate than Krylov subspace methods. The new method can be viewed as a general Y-Delta reduction approach[B1] and have been used for RF spiral inductor modelings[J2].

Although many progresses have been made in this field in the past two decades, there are still many outstanding problems yet to be solved. Among them are (1) reduction of interconnect circuits with massive ports, which are very common in practical VLSI systems (like memory, DSP ICs); (2) wideband reduction of parasitic circuits for analog/mixed-signal/RF/millimeter circuits, where accuracy is required for the wide frequency bandwidth, (3) passive reduction of linear dynamic systems with different input and outputs, which canât be solved by existing projection based framework, (4) Efficient variational or statistical reduction techniques consider process variations (5) reduction technique for general nonlinear circuits.

Invited Presentations

Dr. Sheldon Tan, Tsinghua University, Beijing, China, âModeling and Simulation of Nanometer Interconnect Circuitsâ, Aug. 23, 2005.
Dr. Sheldon Tan, Cadence Design Systems, Inc., San Jose, CA, âPassive model order reduction and terminal reduction for interconnect circuits with multiple terminalsâ, Nov. 9, 2005.
Dr. Sheldon Tan, University of Tokyo, Tokyo, Japan, âHierarchical model order reduction for wideband interconnect modelingâ, Jan. 25, 2006.
Dr. Sheldon Tan, Cadence Design Systems, Inc., San Jose, CA, âTermMerg: Fast terminal reduction for interconnect circuits with multiple terminalsâ, Feb. 7, 2006.
Dr. Sheldon Tan, Cadence Design Systems, Inc., San Jose, CA, "An extended SVD-based terminal and model order reduction algorithm", June 12, 2006.
Dr. Sheldon Tan, System LSI Design Workshop, Fukuoka, Japan, "Recent Advance in Terminal and Model Order Reduction for Interconnect Circuits", Sept. 9, 2006.
Dr. Sheldon Tan, Electrical Engineering Colloquium, UCR, "Modeling and Simulation of Sub-90nm Interconnect Circuits: Problem, Solution and Future Challenges", May 7, 2007.
Dr. Sheldon Tan, Beijing JiaoTong University, Beijing, China, "Modeling and analysis of 90nm VLSI Interconnects: problem, solutions and future challenges", July 5, 2007.
Dr. Sheldon Tan, Tsinghua University, Beijing, China, "Passive compact modeling of inductively coupled interconnect circuits by projection-based balanced truncation", July 20, 2007.
Dr. Sheldon Tan, Cadence Design Systems Inc, San Jose, CA, "Numerical solution of eigenvalue problems and singular value decomposition (SVD)", March 21, 2008.
Dr. Sheldon Tan, Cadence Design Systems Inc, San Jose, CA, "Partitioning-based reduction method for large linear network analysis", June 18, 2008.
Dr. Shedlon Tan, Workshop of SoC Design Methodologies, National Tsing-Hua Univ., Tsin-Chu, Taiwan, "Efficient reduction-based methods for on-chip power grid network analysis", Sept. 9, 2008.
Dr. Sheldon Tan, Cadence Design Systems Inc, San Jose, CA, "Hierarchical Reduction Based Analyses Method For Large Power Delivery Networks", Oct. 9, 2008.
Dr. Sheldon Tan, International Conference on Solid-State and Integrated Circuit Technology (ICSICT'08), Beijing, "A Survey of RLCK Reduction and Simulation Methods by Fast Truncated Balanced Realization", Oct. 21, 2008.
Dr. Sheldon Tan, Rice University, ECE Department, TX, "Decentralized Model Order Reduction and Simulation of Linear Networks with Massive Ports", Jan. 29, 2009.
Dr. Sheldon Tan, Cadence Design Systems Inc, San Jose, CA, "Performance Comparison for Reduction-Based P/G Network Analysis Methods", Feb 26, 2009.
Dr. Sheldon Tan, VirageLogic Corporation, Fremont, CA, "Boost Post-layout Verification Efficiency by Circuit Complexity Reduction", May 5, 2009.
Dr. Sheldon Tan, CEC Huada Electronic Design Co., Ltd, Beijing, China, âBoost Post-layout Verification Efficiency for Analog Circuits by Compact Modeling of Parasiticsâ, July 24, 2009.

Software package releases

The UiMOR program: UC Riverside Model Order Reduction Suite Tool, which can perform wideband complexity reduction and generate SPICE-compatible netlists. Relevant Publications

Relevant publications

Books

B1. Zhanhai Qin, Sheldon X.-D. Tan and Chung-Kuan Cheng, Symbolic Analysis and Reduction of VLSI Circuits, Springer Publisher, 2005, ISBN: 0-387-23904-9; e-ISBN: 0-387-23905-7.
B2. Sheldon X.-D. Tan and Lei He, Advanced Model Order Reduction Techniques for VLSI Designs, Cambridge University Press, 2007, ISBN-13 978-0-521-86581-4, ISBN-10 0-521-86581.

Journal publications

J1. S. X.-D. Tan, "A general hierarchical circuit modeling and simulation algorithm", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 3, pp. 418-434, March 2005.
J2. Z. Qi,, H. Yu, P. Liu, S. X.-D. Tan, L. He, "Wideband passive multi-port model order reduction and realization of RLCM circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (TCAD), vol. 25, No. 8, pp. 1496-1509, Aug. 2006.
J3. P. Liu, S. X.-D. Tan, B. Yan, B. McGaughy, "An efficient terminal and model order reduction algorithm", Integration, the VLSI Journal, vol.41, no.2, pp.210-218, Feb. 2008. (online permanent DOI link)
J4. B. Yan, S. X.-D. Tan, B. McGaughy, "Second-order balanced truncation for passive-order reduction of RLCK circuits", IEEE Transaction on Circuit and System II (TCAS-II), vol. 55 no. 9, pp. 942-946, Sept 2008.
J5. N. Mi, B. Yan, S. X.-D. Tan, "Multiple block structure-preserving reduced order modeling of interconnect circuits", Integration, The VLSI Journal, vol. 42, no. 2, pp.158-168, 2009, (online permanent DOI link)
J6. D. Li, S. X.-D. Tan, L. Wu, "Hierarchical Krylov subspace based reduction of large interconnects", Integration, The VLSI Journal, vol. 42, no.2, pp193-202, 2009. (online permanent DOI link)
J7. H. Yu, C. Chu, Y. Shi, D. Smart, L. He and S. X.-D. Tan, "Fast analysis of large scale inductive interconnect by block structure preserved macromodeling", IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), (in press).
J8. D. Li, S. X.-D. Tan, "Fast analysis of on-chip power grid circuits by extended truncated balanced realization method", IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science, vol. E92-A, no. 12, pp.3061-3069, 2009.
J9. S. X.-D. Tan, B. Yan and H. Wang, "Recent advance in non-Krylov subspace model order reduction of interconnect circuits", Tsinghua Science and Technology, (in press) (invited)
J10. B. Yan, S. X.-D. Tan and J. Fan, "Passive rational interpolation based reduction via Caratheodory extension for general systems", IEEE Transaction on Circuit and System II (TCAS-II), (in press).

Conference publications

C1 S. X.-D. Tan, "A general s-domain hierarchical network reduction algorithm", Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), San Jose, CA, pp. 650-657, Nov. 2003.
C2 H. Yu, L. He and S. X.-D. Tan, "Compact macro-modeling for on-chip RF passive components"Â, Proc. IEEE International Conference on Communications, Circuits and Systems, Chengdu, vol. 2, pp. 199-202, China, 2004 .
C3 Z. Qi , S. X-.D. Tan, H. Yu , L. He and P. Liu, "Wideband modeling of RF/analog circuits via hierarchical multi-point model order reduction", Proc. Asia South Pacific Design Automation Conference (ASP-DAC'05), pp.224-229. Shanghai, China, Jan. 2005.
C4 H. Yu, Z. Qi, L. He and S. X.-D. Tan, "A wideband hierarchical circuit reduction for massively coupled interconnects", Proc. Asia South Pacific Design Automation Conference (ASP-DAC'05), pp.111-114, Shanghai, China, Jan. 2005.
C5 P. Liu, Z. Qi and S. X.-D. Tan, "Passive hierarchical model order reduction and realization of RLCM circuits", Proc. Int. Symposium. on Quality Electronic Design (ISQED'05), pp. 603-608, San Jose, CA, March 2005.
C6 P. Liu, Z. Qi, A. Aviles, S. X.-D. Tan, "A general method for multi-port active network reduction and realization", IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), pp.7-12, San Jose, CA, Sept., 2005.
C7 H. Yu, L. He, S. X.-D. Tan, "Block structure preserving model reduction", IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), pp.1-6, San Jose, CA, Sept., 2005.
C8 P. Liu, S. X.-D. Tan, H. Li, Z. Qi, J. Kong, B. McGaughy, L. He, "An efficient method for terminal reduction of interconnect circuits considering delay variations", Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), pp. 821-826, San Jose, CA, Nov. 2005.
C9 P. Liu, S. X.-D. Tan, B. McGaughy, L. Wu, "Compact reduced order modeling for multiple-port interconnects", Proc. Int. Symposium. on Quality Electronic Design (ISQED'06), pp.413-418, San Jose, CA, March 2006.
C10 P. Liu, S. X.-D. Tan, B. Yan, B. McGaughy "An extended SVD-based terminal and model order reduction algorithm", IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), pp.44-49, San Jose, CA, Sept., 2006.
C11 J. Fan, N. Mi, S. X.-D. Tan, "Variational compact modeling and simulation for linear dynamic systems", IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), pp.17-22, San Jose, CA, Sept., 2006.
C12 B. Yan, S. X-.D. Tan, P. Liu, B. McGaughy, "Passive interconnect macromodeling via balanced truncation of linear systems in descriptor form", Proc. Asia South Pacific Design Automation Conference (ASP-DAC'07), pp. 355-360, Yokohama City, Japan, Jan. 2007.
C13 B. Yan, P. Liu, S. X.-D. Tan, B. McGaughy, "Passive modeling of interconnects by waveform shaping", Proc. Int. Symposium. on Quality Electronic Design (ISQED'07), pp.356-361, San Jose, CA, March 2007.
C14 N. Mi, B. Yan, S. X.-D. Tan, J. Fan, H. Yu "General block structure-preserving reduced order modeling of linear dynamic circuits", Proc. Int. Symposium. on Quality Electronic Design (ISQED'07), pp. 633-638, San Jose, CA, March 2007.
C15 J. Fan, N. Mi, S. X.-D. Tan, Y. Cai and X. Hong, "Statistical model order reduction for interconnect circuits considering spatial correlations", Proc. Design, Automation and Test in Europe (DATE'07), pp. 1508-1513, Nice, France, April 2007.
C16 B. Yan, S. X-.D. Tan, P. Liu, B. McGaughy, "SBPOR: second-order balanced truncation for passive model order reduction of RLC circuits"Â, Proc. IEEE/ACM Design Automation Conference (DAC'07), pp.158-161, San Diego, CA, 2007.
C17 D. Li, S. X.-D. Tan, "Hierarchical Krylov subspace reduced order modeling of large RLC circuits", Proc. Asia South Pacific Design Automation Conference (ASP-DAC'08), pp.170-175, Seoul, Korea, Jan. 2008.
C18 D. Li, S.X.-D. Tan, B. McGaughy, "ETBR: Extended truncated balanced realization method for on-chip power grid network analysis", Proc. Design, Automation and Test in Europe (DATE'08), pp.432-437, Munich, Germany, March 2008.
C19 B. Yan, L. Zhou, S. X.-D. Tan, J. Chen, B. McGaughy, "DeMOR: Decentralized model order reduction of linear networks with massive ports", Proc. IEEE/ACM Design Automation Conference (DAC'08), pp. 409-414, Anaheim, CA, 2008.
C20 B. Yan, H. Wang, S. X.-D. Tan, "Survey of RLCK reduction and simulation methods by fast truncated balanced realization", Int, Conf. Solid State and Integrated Circuit Technology (ICSICT'08), pp. H1.3, Beijing, China, Oct. 2008. (invited)
C21 H. Yu, X. Liu, H. Wang, S. X.-D. Tan, "Fast analog mismatch analysis by an incremental and stochastic trajectory piecewise linear macromodel", Proc. Asia South Pacific Design Automation Conference (ASP-DAC'10), pp.211-216, Taipei, Taiwan, Jan. 2010.
C22 H. Wang, S. X.-D. Tan, G. Chen, "Wideband reduced modeling of interconnect circuits by adaptive complex-valued sampling method", Proc. Asia South Pacific Design Automation Conference (ASP-DAC'10), pp.31-26, Taipei, Taiwan, Jan. 2010.
C23 B. Yan and S. X.-D. Tan, G. Chen, Y. Cai, "Model reduction of interconnects via double gramians approximation", Proc. Asia South Pacific Design Automation Conference (ASP-DAC'10), pp. 25-30, Taipei, Taiwan, Jan. 2010.

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Modeling and Analysis for Accelerating Aging Effects for Copper Interconnect ICs

jbradfield — Thu, 01 Aug 2019 22:01:58 +0000

Modeling and Analysis for Accelerating Aging Effects for Copper Interconnect ICs jbradfield Thu, 08/01/2019 - 15:01 More Project August 01, 2016

Principle Investigators

Dr. Sheldon Tan (PI)

Graduate Students

Current Students

Taeyoung Kim
Chase Cook
Zeyu Sun
Hengyang Zhao

Graduate Students (graduated)

Dr. Xin Huang (Oracle Corp)

Industry Liaisons

Dr. Mehul Shroff, NXP Semiconductor, Inc.
Dr. Ertugrul Demircan, NXP Semiconductor, Inc.

Funding

We appreciate the following funding agencies for their generous supports of this project.

Defense Advanced Research Projects Agency (DARPA) (HR0011-16-2-0009), "Advanced Modeling and Analysis for Accelerating Effects of Electromigration and Stress Migration for Copper Interconnects of ICs", $ 462,644, Feb 11th 2016 to Aug 11th 2018 (30 months). Single PI.

Awards

Project Descriptions

Background

Reliability is becoming a limiting constraint in high-performance nanometer VLSI chip designs due to the high failure rates in deep submicron and nanoscale devices. It was expected that the future chips will show sign of reliability-induced age much faster than the previous generations. Among of many reliability effects, electromigration (EM)-induced reliability has become a major design constraint due to aggressive transistor scaling and increasing power density.

Electromigration (EM) is a physical phenomenon of the oriented migration of metal (Cu) atoms along a direction of applied electrical field due to the momentum exchange between atoms and the conducting electrons. Migration of atoms results in metal density depletion or accumulation, which leads to build-up of hydrostatic stresses across the conductor. EM can degrade both global interconnects such as power grid networks and signal wires when the current densities are sufficiently high (about 1MA/cm^2). However, the power grid networks are more susceptible to EM effects due to the conduction of unidirectional currents.

The motivations of this project

This project is to develop new physics-based predicted electromigration (EM) and stress migration (SM) models, and fast analysis methods which can work on extreme stressing conditions targeting to the back end of the line (BEOL), technical Area 2. We will focus on following thrusts.

Firstly, we are looking the closed form solutions to the fundamental stress-based differential equations (Korhonen's equation) and perform simulation against numerical results. For SM models, we plan to apply the finite difference method and model reduction techniques to obtain the compact models of the stress due to thermo-mechanical dynamics
Secondly,we are going to perform the tree decompositions (into simple wires) first and then finding the closed form solutions to the coupled fundamental stress-based differential equations (Korhonen's equation) and perform simulation against numerical results.
Thirdly,we are going to develop the closed form expressions from the solutions of fundamental stress-based differential equations (Korhonen's equation) considering time-varying current densities and temperature changes.

We expect the following results coming from this research:

The project will mainly focus on the sub-phase A of this IRIS Phase III program, with the goal of developing advanced physics-based EM/SM models.
We will seek to develop new physics-based predictable EM and SM models and fast failure assessment techniques for accelerated aging and wear-out of copper interconnects.
We will verify the proposed models against numerical analysis methods using COMSOL.
We work with industry partners to validate our models (NXP).

Research tasks and objectives

The first task is to develop physics-based EM and SM models for dual damascene copper wires. its objective is to develop the physics-based EM models for single dual damascene copper wire. The second task is to develop physics-based EM models for copper interconnect trees. Its objective is to develop the physics-based EM models for more complicated dual damascene copper interconnect wires. The third task is to develop physics-based EM models for dual damascene copper wires consider time-varying temperature and current densities. Its objective is to develop the physics-based EM models for dual damascene interconnect wires considering the time-varying temperature and current densities.

Features of the proposed methods

Address the long-term thermal-sensitive reliability issues such EM, SM, thermal cycling effects by analysis thermal and current density effects on multi-branch interconnect trees.
New physics-based EM assessment techniques which is more accurate and faster than traditional methods.
New physics-based EM model working with high stress condition (high temperature and high current density) for EM acceleration.
The new EM and SM (stress migration) models can be used for both normal chip operations and extreme stressing conditions.
The new EM model can be applied to vulnerable structures and more complex power grid and get accurate information for time to fail.

Invited Presentations by Dr. Sheldon Tan and collaborators

Tutorial Presentations by Dr. Sheldon Tan

Software Download

The developed EM models in matlab codes are shared in the github at physics-based EM assessment analysis codes and documents

Publications

Journal publications

J1 X. Huang, V. Sukharev, J.-H. Choy, M. Chew, T. Kim, S. X.-D. Tan, "Electromigration assessment for power grid networks considering temperature and thermal stress effects", Integration, The VLSI Journal, , Volume 55, September 2016, Pages 307-315, ISSN 0167-9260, https://doi.org/10.1016/j.vlsi.2016.04.001.

J2 K. He, X. Huang, S. X.-D. Tan, "EM-based on-chip aging sensor for detection of recycled ICs", IEEE Design & Test, pp.56-64, June, 2016.

J3 X. Huang, V. Sukharev, T. Kim, S. X.-D. Tan, "Dynamic electromigration modeling for transient stress evolution and recovery under time-dependent current and temperature stressing," Integration, the VLSI Journal, Available online 12 November 2016, ISSN 0167-9260, https://doi.org/10.1016/j.vlsi.2016.10.007.

Conference publications

C1 Z. Sun, E. Demircan, M. Shroff, T. Kim, X. Huang, S. X.-D. Tan, "Voltage-based electromigration immortality check for general multi-branch interconnects", Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD'16), Austin, TX, Nov. 2016.

C2 T. Kim, Z. Sun, J. Gaddipati, H. Wang, H. Chen, S. X.-D. Tan, "Dynamic reliability management for near-threshold dark silicon processors", Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD'16), Austin, TX, Nov. 2016. (Invited)

C3 L. Xu, H. Wang, S. X.-D. Tan, C. Zhang, Y. Yuan, K. Huang, Z. Zhang, "Distributed model predictive control for dynamic thermal management of multi-core systems", Int., Conf. Solid State and Integrated Circuit Technology (ICSICT'16), Hangzhou, China, Oct. 2016.

C4 J. Wan, H. Wang, J. He, S. X.-D. Tan, Y. Cai, S. Yang "A fast full-chip static power estimation method", Int., Conf. Solid State and Integrated Circuit Technology (ICSICT'16), Hangzhou, China, Oct. 2016.

C5 S. Wang, H. Zhao, S. X.-D. Sheldon Tan and M. Tahoori, "Recovery-aware proactive TSV repair for electromigration in 3D ICs", Proc. Design, Automation and Test in Europe (DATE'17), Lausenne, Switzerland, March 2017.

C6 X. Wang, H. Wang, J. He, S. X.-D. Tan, Y. Cai and S. Yang, "Physics-based electromigration modeling and assessment for multi-segment interconnects in power grid networks", Proc. Design, Automation and Test in Europe (DATE'17), Lausanne, Switzerland, March 2017.

C7 Y. Yao, T. Kim H. Chen, H. Wang, E. Tlelo-Cuautle and S. X.-D. Tan, "Comprehensive detection of counterfeit ICs via on-chip sensor and post-fabrication authentication policy", International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD'17) Giardini Naxos - Taormina, Italy, June 2017.

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